1. Field of the Invention
This invention relates to an improved method for bonding leads of semiconductor devices, such as integrated circuits, to conductive members using a eutectic composition of gold and tin and to the lead bonding structure obtained with the method. More particularly, it relates to such a method and structure in which the amount of tin reacting with gold is limited and the formation of brittle intermetallic compositions is avoided, thus increasing reliability at elevated temperatures.
2. Description of the Prior Art
Alloys of tin and gold are widely used in the bonding of semiconductor devices to conductive members. For example, bonding processes employing a eutectic composition of 80 weight percent gold and 20 weight percent tin are disclosed in Kadelburg, U.S. Pat. Nos. 3,158,471, issued Nov. 24, 1964 and Ainslie et al., 4,418,857, issued Dec. 6, 1983. Gold-tin lead bonding is commonly used in the semiconductor industry in the form described in VLSI Technology (Sze, S. M., ed.), McGraw-Hill, 1983, page 562. As disclosed there, gold bumps on the integrated circuits are bonded to tin coated copper tape. While this structure is heated to 280.degree. C. to form an 80-20 gold-tin eutectic composition, the formation of brittle intermetallics in this process as conventionally employed cannot be avoided, because the quantity of tin reacting with the gold is unlimited or uncontrollable, which will be more fully explained below.
The process as described in the above text is generally satisfactory for use with many integrated circuits, but it suffers from low reliability for on board applications at elevated temperatures, such as above 125.degree. C., especially in combination with thermal cycling and/or mechanical shock and vibration. Disadvantages associated with this process include potential reliability problems resulting from a combination of elevated temperatures, mechanical shocks and/or thermal cycles, due to the creation of brittle intermetallics, and a difficult-to-control bonding process.
The development of gate arrays and similar very large scale integration (VLSI) and very high speed integrated circuit (VHSIC) devices with leads numbering in the hundreds has resulted in increased demands on device bonding technology and makes usage of a simultaneous bonding process an economic and technical necessity. Such devices having an increased number of leads require a higher reliability of bonding, a fully controllable process of achieving a metallurgical bond and simultaneously, an increase in the density of bonding pads on the integrated circuit chips. The requirements for such VLSI and VHSIC devices are described more fully in Marshall, J. F. and Sheppard, R. P., "New Applications of Tape Bonding for High Lead Count Devices", Semiconductor Processing, ASTM STP 850. (Gupta, D. C., ed.) American Society for Testing and Materials, 1984.
A proposed approach for meeting the demands for bonding such chips having a high number of leads is through thermocompression or ultrasonic bonding of gold bumps on the chips with gold spots on a tape. Thermocompression or ultrasonic bonding provides a good electrical contact, bu sometimes produces a poor metallurgical bond. Poor metallurgical bonds are very difficult to detect and can result in a significant reliability problem due to premature failure of such bonds in use of the chips.
Another lead bonding process that has been employed in the prior art is the use of controlled collapse solder bumps. However, problems have been encountered adapting the controlled collapse technique to surface mounted devices, since the controlled collapse solder bumps and the tin-lead alloys used for surface mounting have the same eutectic points, and with reliability of the controlled collapse solder bumps at elevated temperatures.
It is also known to provide a hermetically sealed semiconductor device package by disposing a gold-tin eutectic alloy preform between a cover and a supporting member for the semiconductor device, and fusing the cover to the supporting member with the preform. Such a process is disclosed, for example, in U.S. Pat. No. 4,232,814, issued Nov. 11, 1980 to Norman. Very reliable sealing is accomplished in this manner, but such a process cannot be used for bonding leads of integrated circuit chips to a conductive substrate.
A similar process is disclosed for backside contact bonding of integrated circuit devices to carrier substrates in VLSI Technology (Sze, S. M., ed.), McGraw-Hill, 1983, page 553. As in the case of package sealing, the use of such preforms is not possible for bonding leads on the front of a integrated circuit chip.